The PSW contains information such as the next instruction address, current condition code, and any system masks for interrupts 37.
#Nasa pc ram 64 bits#
A program status word (PSW), 64 bits in length, is used to help control interrupts. Thus, processing is accelerated and achieves the performance noted above 36. As a result, the registers are faster than those used on Gemini and Apollo and, since they are available in large sets, can be used to store intermediate results of calculations without having to access core memory. Semiconductor memories are used in the registers instead of discrete components. One set of eight 32-bit registers is for floating point operations 35. Two sets of eight 32-bit registers are available for fixed-point arithmetic. Instructions using floating-point take longer to execute than fixed-point arithmetic, and adding is still faster than multiplying but average speed for the machine is 480,000 instructions per second, compared with 7,000 instructions per second in the Gemini computer 34.
Floating-point arithmetic is done with 32-, 40- and 64-bit words, although the latter are limited to addition and subtraction 33. Fixed-point arithmetic, done using fractional numbers stored in two's complement form, also uses 16- and 32-bit lengths. Instructions can be either 16 or 32 bits in length. The circuits are on boards that can be interchanged as units. The TTL gates are arranged in medium-scale integration (MSI) and large-scale integration (LSI) configurations 32. The AP-101 is built using transistor-transistor logic (TTL) semiconductor circuits as the basic building block.
Box 4-1: IBM AP-101 Central Processor and Memory Hardware Shuttle computers make extensive use of standard ICs. The fifth computer is the Backup Flight System computer. A block diagram of the hardware that makes up the Shuttle Data Processing System. The AP-101 has room for up to 2,048 microinstructions, 48 bits in length 31. Microcode is a set of primitives that can be combined to create new logic paths in the hardware. Since the execution of instructions is dependent on microcode, rather than hardware only, the instruction set could be changed somewhat. Although one of the reasons for choosing the AP-101 was its familiar instruction set, some modifications were necessary for the Shuttle version. The central processor in each case is the same, but the IOP is adapted to the particular application. The AP-101 version, which is an upgraded AP-1, has since been used in the B-52 and B-1B military aircraft and the F-8 digital fly-by-wire experimental aircraft. IBM announced the 4Pi in 1966, so by the early 1970s, when Shuttle procurement was complete, the machine had had extensive operational use 30.
#Nasa pc ram series#
The AP-101 has the same type of registers and architecture used in the IBM System 360 and throughout the 4Pi series 29. Each one is an IBM AP-101 central processing unit (CPU) coupled with a custom-built input/output processor (IOP). General-Purpose Computers NASA uses five general-purpose computers in the Shuttle. Together, they are a model for future avionics developments. Each is a substantial improvement over similar systems in any previous spacecraft. Chapter Four - Computers in the Space Shuttle Avionics System - The DPS hardware configuration The DPS hardware in the shuttle avionics system consists of four major components: general-purpose computers, the data bus network, the multifunction cathode ray tube display system, and the mass memory units.
Computers in Spaceflight: The NASAExperience
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